Welcome to the Muon Tracker PLD PAGE






                        1. Documentation

1.1   AMU Block Diagram
1.2   ADC_DCM readout Block Diagram
1.3   DCM DATA FORMAT
1.4   AMU/ADC
1.5   ALTERA 10K
1.6   TIMING Diagram 1a
1.7   TIMING Diagram 1b
1.8   Recorded timing for AMU-adc   0-4us
1.9   Recorded timing for AMU-adc   0-750ns
1.10 FPGA SERIAL STRING doc
1.11 schematics of the PLD
1.12 MUON Tracker FPGA DOC
1.13   TIMING Diagram 1c     NEW

                       2. Hardware Designs

                        2.1 Clink-pc board
                        2.2 Clink-pc PLD
                        2.3 Clink-pc PLD pin outs
 

3. Software
 

3.1FPGA VER 1 (4/10/00)   (rev 1)

3.2FPGA VER 2 (4/11/00)   (rev 2)
    cav dav are inverted and green led it tied to lev1

3.3FPGA VER 3 (4/11/00)   (rev 3)
    cav and dav returned to rev1 setting  and more header information is added ( event counter is corrected, all 4 cell numbers are added to return event 1 cells , user word returns 0769, last word in packet is set to 0000 with cav on dav off) all clocks are now synched  to Bclk rising edge.  e72 is lev1
!!!!(found an error in arcnet serial default string setup)

3.4FPGA VER 4 (4/14/00)   (rev 4)
    TEST VERSION!!! (all amu data inputs are removed and set to a fixed value)  amu1 = 1000 amu2= 2000 amu3 = 3000 amu4=4000. and arcnet serial stream FIXED using default string.

3.5FPGA VER 5 (4/14/00)   (rev 5)
   TEST VERSION!!!  same as ver4 except DCM OUTPUT CLOCK inverted.

3.6FPGA VER 6 (4/14/00)   (rev 6)
   TEST VERSION!!!   same as VER 4 except  USER BIT1 is used to fake a FSC. to collect data with the memory manager.

3.7FPGA VER 7 (4/17/00)   (rev 7)
   TEST VERSION!!!   FIXED reset problem, FIXED dcm readout (140 words), FAKE dcm data = wr_Add  +1 , rd_add + 2 , evntcnt + 3,  mem addr + 4.  (user bit 1 still FSC) .
new test points   e12 = AZ, e13 = ICS, e14 =amp_rst, e15=load, e10 = r_en, e9 = dat_av(internal signal).

3.8FPGA VER 8 (4/17/00)   (rev 8)
   BUS_EN  corrected, amu data restored to correct setting, rst fixed so that no garbage is added to dcm output.

3.9FPGA VER 9 (4/17/00)   (rev 9)
   DCM_DATA out now stet up for amu1a amu1b amu2a amu 2b   FIXED dcm readout (140 words), e12 = clk_en

3.10 FPGA VER 10 (4/27/00)   (rev 10)   (BAD)
   DCM_DATA out now has 8 user words and a checksum word (not correct value)

3.11 FPGA VER 11 (4/27/00)   (rev 11)
   DCM_DATA out now has 8 user words and a checksum word (not correct value)  (FIXED VERSION 10)

3.12 FPGA VER 12 (4/28/00)   (rev 12)
   ALL FIFO's now implemented in LC's instead of EAB's  (enough memory for all five events)

3.13 FPGA VER 13 (4/28/00)   (rev 13)
   DCM DATA out garbage removed and main AMU address fifo implemented in eabs and the rest use LC's

3.14 FPGA VER 14 (5/03/00)   (rev 14)
   AMU memory manager redesigned for better lev1 handling.  Clink output on pin 18 and 17 set high.  all five event memory's installed and operating.  cell's used in data stream now reported in dcm output for all events.

3.15 FPGA VER 15 (5/03/00)   (rev 15)
   Data output sends all 4 samples per event.

3.16FPGA VER 16 (5/03/00)   (rev 16)
   removed event fifo replaced with comb logic, removed extra word from dcm output, reset modified for async reset.
    ver 16 jbc file cnt_pld16.jbc

3.17FPGA VER 17 (5/04/00)   (rev 17)
   minor changes to the GTM input section.

3.18FPGA VER 18 (5/08/00)   (rev 18)
   changes to level 1 handling routine, cell address used in conversion also reported in user word. only responds to endat0

3.19FPGA VER 19 (5/09/00)   (rev 19)
   TEST VERSION   removed event 5 memory  and implemented  all fifo's in EAB's.

3.20FPGA VER 20 (5/09/00)   (rev 20)
   CLK distribution modified from ver. 19.

3.21FPGA VER 21 (5/10/00)   (rev 21)
   Same as ver 20 (NOT USING Quartus settings).

3.22FPGA VER 22 (5/11/00)   (rev 22)
   Fixed AMU cell selecting manager.

3.23FPGA VER 23 (5/11/00)   (rev 23)
   User words now have cells used in order of AD  conversion (0-7).

3.24FPGA VER 24 (5/11/00)   (rev 24)
   the samples now selected are  blk+x where  x=41 x=35 x=29 x=22    (old value x=41 x=40 x=38 x=36).

3.25FPGA VER 25 (5/12/00)   (rev 25)
   Fixed level1 handling so that one amu cell is used instead of two.

3.26FPGA VER 26 (5/15/00)   (rev 26)
   level 1 restricted to 1 event at a time.

3.27FPGA VER 27 (5/15/00)   (rev 27)
   DCMoutput manager modified and lev1 changed.

3.28FPGA VER 28 (5/16/00)   (rev 28)
    This is a test version that sends the address that is being written to the amu cells to the dcm output when endat is enabled new test points
e9 = dataav  e10= used e15 =tlev1 e14 = lev1

3.29FPGA VER 29 (5/16/00)   (rev 29)
  TEST VERSION same as 3.28 changed cell append section and dcm readout section.

3.30FPGA VER 30 (5/18/00)   (rev 30)
  TEST VERSION!!!   D0-D5  on output data = amucell address  D8-D16 = memory read #.

3.31FPGA VER 31 (5/18/00)   (rev 31)
  TEST VERSION!!!   D0-D5  on output data = amucell address  D8-D16 = memory read #. fixed bugs found in ver 30

3.32FPGA VER 32 (5/18/00)   (rev 32)
  TEST VERSION!!!   Fixed USED AMU CELL # MUX counter. Modified method used to save the numbers.

3.33FPGA VER 33 (5/19/00)   (rev 33)
  TEST VERSION!!!   USED To test AUX ports.  file 1 = endat0 file 2= endat1   ... endat0 board must be hooked to dcm output.   file 2 = cntl_pld33_aux.pof

3.34FPGA VER 34 (5/19/00)   (rev 34)
  TEST VERSION!!!   SAME as ver 33 with endat bug fixed    file 2 = cntl_pld34_aux.pof

3.35FPGA VER 35 (5/19/00)   (rev 35)
  FULL version responds to endat0.

3.36FPGA VER 36 (5/24/00)   (rev 36)
  TEST version responds to endat0. edited some timing problems.

3.37FPGA VER 37 (5/24/00)   (rev 37)
  TEST version responds to endat0. edited some timing problems.

3.38FPGA VER 38 (5/25/00)   (rev 38)
  TEST version responds to endat0. edited some timing
problems.

3.39FPGA VER 39 (5/25/00)   (rev 39)
  FULL version responds to endat0. event 5-10-15... has fffff for output.

3.40FPGA VER 40 (5/26/00)   (rev 40)
  FULL version responds to endat0.
     dcm data bit 12-16 has memory address for each event.  timing is now controlled by dav line.

3.41FPGA VER 41 (5/26/00)   (rev 41)
  FULL version responds to endat0.
        same as ver 40 DAV TFC in inverted.

3.42FPGA VER 42 (5/30/00)   (rev 42)
  FULL version responds to endat0. event 5-10-15. has ff777
timing fixed in amu cell storage algorithm.
 

3.43FPGA VER 43 (5/30/00)   (rev 43)
  FULL version  endat1 aux port disabled. test points changed. e9 = tfc16  e7 = tfc17 e10 = tfc18
e20=  tfc19 e19 = tfc20

3.44FPGA VER 44 (5/31/00)   (rev 44)
  FULL version  endat1 aux port disabled. event 5 is put back in place. new testmode feature added. and more timning fixes.
test modes.   userbit 1  0 = off , 1 = on   has memory location in bit 8-16
  toggle user bi t2 for other modes.
     mode 00 = amu cells  mode 01 = ev cell stored readout
    mode  02 = ev cntr location   mode 03 = part of data

3.45FPGA VER 45 (5/31/00)   (rev 45)
  FULL version  endat1 aux port disabled.  fifo implemented in EAB

3.46FPGA VER 46 (6/7/00)   (rev 46)
  TEST version  endat1 aux port disabled.  fifo implemented in EAB and first 2 bits of data word = order of conversion.

3.47FPGA VER 47 (6/7/00)   (rev 47)
  TEST version  endat1 aux port disabled.  fifo implemented in EAB. Data for amuadc 1  and 2 has been replaced by test data.  0 = write address  1= read address.

3.48FPGA VER 48 (6/8/00)   (rev 48)
  TEST version  endat1 aux port disabled.  fifo implemented in EAB. Fixed a glitch found in the new fifo.

3.49FPGA VER 49 (6/8/00)   (rev 49)    !!TEST VERSION!!
  TEST version  endat1 aux port disabled.  fifo implemented in EAB. each level1 will generate 16 consecutive samples. 4 endat  are required after each lev1.   every 5th endat will generate test data.'

3.50FPGA VER 50 (6/8/00)   (rev 50)   SAME AS VER 48 BUT WITH VER 49 EMBEADED.
  TEST version  endat1 aux port disabled.  fifo implemented in EAB. Fixed a glitch found in the new fifo.

3.51FPGA VER 51 (6/12/00)   (rev 51)
 Reset now move to modebit3.

3.52FPGA VER 52 (6/14/00)   (rev 52)
 Fifo now implemented in LC's and 5th event memory location put back.

3.53FPGA VER 53 (6/16/00)   (rev 53)
 Full version all can handle 5 events (every 5 event will generate 0xffff)

3.54FPGA VER 54 (6/16/00)   (rev 54)
 Same as Ver 53 but fifo is implemented using a simple LC design.

3.55FPGA VER 55 (6/16/00)   (rev 55)
 FULL 5 event and final memory model.
 

3.56FPGA VER 56 (6/19/00)   (rev 56)
 FULL VERSION.   code cleanup.

3.57FPGA VER 57 (6/19/00)   (rev 57)
 FULL VERSION.   FIXED ERROR IN VER 56.

3.58FPGA VER 58 (6/19/00)   (rev 58)
 fixing amu timing

3.59FPGA VER 59 (6/20/00)   (rev 59)
 fixing amu timing

3.60FPGA VER 60 (6/21/00)   (rev 60)
 FIXED FULL SCALE COUNT HANDLING.

3.61FPGA VER 61 (6/21/00)   (rev 61)
 Total recomplile with maxplusII.

3.62FPGA VER 62 (6/22/00)   (rev 62)
 new empty fifo setup

3.63FPGA VER 63 (6/22/00)   (rev 63)
 new empty fifo setup II.

3.64FPGA VER 64 (6/22/00)   (rev 64) (back up 6/23/00)
 general cleanup and simple modifications.

3.65FPGA VER 65 (6/23/00)   (rev 65)
 2 us delay added between FSC and next conversion.

3.66FPGA VER 66 (6/26/00)   (rev 66)
 Amu timing changed.

3.67FPGA VER 67 (6/28/00)   (rev 67)
 VER 64 with endat1 campabilites. And ver 67 slave FPGA_ver67S.

3.68FPGA VER 68 (6/28/00)   (rev 68)
 Restore back to ver 64
 

3.69FPGA VER 69 (6/28/00)   (rev 69)
 Stop writting amu cell after LEV1

3.70FPGA VER 70 (6/28/00)   (rev 70)  NEW VER 70 master FPGA_ver70m
 VER 64 with endat1 campabilites. And ver 67 slave FPGA_ver70S.

3.71FPGA VER 71 (6/28/00)   (rev 71)
 Stop writting amu cell after LEV1and does not read digital data from amu

3.72FPGA VER 72 (6/30/00)   (rev 72)
 ICS  has been modified.

3.73FPGA VER 73 (6/30/00)   (rev 73)
 DB_rst and CMP_rst has been modified

3.74FPGA VER 74 (6/30/00)   (rev 74)
 RENA  changed and wren internal sig changed

3.75FPGA VER 75 (7/6/00)   (rev 75)
 Back to ver 64

3.76FPGA VER 76 (7/6/00)   (rev 76)
 ICS changed and rena moved by 25ns

3.77FPGA VER 77 (7/6/00)   (rev 77)
 DB_rst and CMP_rst has been modified

3.78FPGA VER 78 (7/7/00)   (rev 78)
  Clean up fix event5 problem and inject set to 0

3.79FPGA VER 79 (7/7/00)   (rev 79)
  inject set to 1

3.80FPGA VER 80 (7/10/00)   (rev 80)
  glitch in fifo fixed.

3.81FPGA VER 81 (7/11/00)   (rev 81)
  AZ set to 0.5us

3.82FPGA VER 82 (7/11/00)   (rev 82)
  STOP WRITE to cells

3.83FPGA VER 83 (7/11/00)   (rev 83)
  STOP reading from AMU

3.84FPGA VER 84 (7/12/00)   (rev 84)
  internal Control signals cleanup

3.85FPGA VER 85 (7/12/00)   (rev 85)
  AMU control signals changed so that  after fsc data is read out first then the next conversion is setup.

3.86FPGA VER 86 (7/13/00)   (rev 86)  TEST version!!!
  first 32 channels  replaced with cell wr address  next 32 samples  with address.

3.87FPGA VER 87 (7/13/00)   (rev 87)
  ver85 with reset fixed.

3.88FPGA VER 88 (7/13/00)   (rev 88)
  can reset FPGA with ARCNET or front switch on control baord.  Serial string is now connected but controls nothing.!!

3.89FPGA VER 89 (7/13/00)   (rev 89)
Master slave in one code.     press reset button to select mode.
green | red  LED  (off | off  = stand alone )  (off | on = master )
( on | off  = slave )  (on | on = slave)
 

3.90FPGA VER 90 (7/13/00)   (rev 90) master2.pof
Master slave version with larger window slave ver90s.pof

3.91FPGA VER 91 (7/14/00)   (rev 91)
  Master uses endat1 to open and close window. salve
ver91slave.pof

3.92FPGA VER 92 (7/14/00)   (rev 92)
  Master uses endat1 to open and close window ver 2.
  save ver92.pof

3.93FPGA VER 93 (7/14/00)   (rev 93)
  Master uses endat1 to open and close window ver 2.
  slave ver93.pof

3.94FPGA VER 94 (7/18/00)   (rev 94)  (stand alone ver)
  Fixed glitch in rep cell address.  set gtm rst high for 5 bclk to rst dcmclk
1 bclk for general reset.

3.95FPGA VER 95 (7/18/00)   (rev 95)  (stand alone ver)
  complex Memory manager replaced with a simple MM.

3.96FPGA VER 96 (7/18/00)   (rev 96)
  VER 95 in master slave mode.
  slave ver96.pof

3.97FPGA VER 97 (7/19/00)   (rev 97)  (stand alone ver)  (does not work)!
     this version has an improved  amu cell generator tha runs of the 2xclk

3.98FPGA VER 98 (8/09/00)   (rev 98)  (MASTER ver)
     Major cleanup of of the schematic and added a 16bit bclk counter and parity check. slave ver98s.pof

3.99FPGA VER 99 (8/11/00)   (rev 99)  (stand alone)
     same as ver 98

3.100 FPGA VER 100 (9/06/00)   (rev 100)  (stand alone)
     NEW memory manager.

3.101 FPGA VER 101 (9/07/00)   (rev 101)  (stand alone)
     cleanup of amu addr generator.

3.102FPGA VER 102 (9/12/00)  (rev 102)  (stand alone)
     mod to the serial string.

3.103FPGA VER 103 (9/18/00)  (rev 103)  (full version)
    serial string enabled.

3.104FPGA VER 104 (9/22/00)  (rev 104)  (full version)
    modified amu cell manager for high data rates

3.105FPGA VER 105 (9/22/00)  (rev 105)  (full version)
    With level 1 counter

3.106FPGA VER 106 (9/22/00)  (rev 106)  (full version)
    Cal data in serial string enabled
 

3.107FPGA VER 107 (9/27/00)  (rev 107)  (full version)
    implemented setting

3.108FPGA VER 108 (9/29/00)  (rev 108)  (full version)
    reduced serial bits to 96 bits 0-79 user bit   80-95 = control

3.109FPGA VER 109 (10/02/00)  (rev 109)  (full version)
    no user wordsl

3.110FPGA VER 110 (10/02/00)  (rev 110)  (full version)
    no user wordsl

3.111FPGA VER 111 (10/02/00)  (rev 111)  (full version)
    no user wordsl

3.112FPGA VER 112 (10/03/00)  (rev 112)  (full version)
    module setup

3.113FPGA VER 113 (10/03/00)  (rev 113)  (full version)
    added delay reg

3.114FPGA VER 114 (10/03/00)  (rev 114)  (DO NOT USE)
    added delay reg    (SKIP)

3.115FPGA VER 115 (10/03/00)  (rev 115)  (full version)
    added extra clk distribution

3.116FPGA VER 116 (10/03/00)  (rev 116)  (full version)
    serial string put back.

3.117FPGA VER 117 (10/05/00)  (rev 117)  (full version)
    reenabled no endat test mode.

3.118FPGA VER 118 (10/17/00)  (rev 118)  (full version)
    5 events enabled and dcm data packet updated

3.119FPGA VER 119 (10/17/00)  (rev 119)  (full version)
    allows for samples to be selected at compile time

3.120FPGA VER 120 (10/18/00)  (rev 120)  (full version)
    FIX For 119

3.121FPGA VER 121 (10/23/00)  (rev 121)  (full version)
    dcm output header detector id flag word and module address
    now have final settings.

3.122FPGA VER 122 (02/06/01)  (rev 122)  (full version)
    samples selected now are 2  6 7 8
 

3.123FPGA VER 123 (02/06/01)  (rev 123)  (full version)
    samples selected now are 3  8 9 10
 

3.124FPGA VER 124 (02/16/01)  (rev 124)  (full version)
    flag word changed so that bit zero = 0 and MAS/SL on bit 1

3.125FPGA VER 125 (04/12/01)  (rev 125)  (full version)
    TIMING FOR AMU CHANGED

3.126FPGA VER 126 (04/12/01)  (rev 126)  (full version)
    TIMING FOR AMU CHANGED AZ and cmp_rst sqeezed
 

3.127FPGA VER 127 (04/13/01)  (rev 127)  (full version)
    TIMING FOR AMU CHANGED AZ and cmp_rst set to 1us
    and after read of the amu (fake read added)
 

3.128FPGA VER 128 (04/17/01)  (rev 128)  (full version)
    TIMING FOR AMU CHANGED AZ and cmp_rst set to .5us
    and during  read of the amu (fake read)
 

3.129FPGA VER 129 (09/24/01)  (rev 129)  (full version)
    Moved from powerview to e products and new samples
 

3.130FPGA VER 130 (09/25/01)  (rev 130)  (full version)
   5 events handled and reduced level1 delay by 4 clocks.
 

3.131FPGA VER 131 (01/14/02)  (rev 131)  (full version)
   READ board status from arcnet (latch data before clocking data out)
 
 3.132FPGA VER 132 (01/22/02)  (rev 132)  (full version)
   READ board status from arcnet (latch data and clock for read dataout)
    Address lines used for arcnet A0 and  A4.
 
  3.133FPGA VER 133 (03/04/04)  (rev 133)  (full version)
  FIX FOR multi event triggering
 
 
 
 

                        4. Useful Links

4.1  ALTERA



Last revision 06/29/1999.
Designed by Jack Fried.