Master Timing & Control System


Contact People:
Sy Rankowitz
Joe Mead
Jack Fried

Last Update: 1/12/99



0.0 Notice

This is a preliminary document and may change without notice over the month of August. Please send any corrections, suggestions and/or general feedback to Jack Fried
.


PHENIX ONLINE SLIDES


1.0 Introduction

This document describes the Phenix Master Timing & Control System. It is contained on one 9U x 400mm eurocard and two 9u x 120mm transition modules. The main function of the system is to provide each of the 32 Timing And Control Modules (Granules) with the following signals: 2.0 Board Level Overview
The phenix 9.4 Mhz clock is derived from the RHIC 9.4 Mhz Clock, jitter is reduced by A PLL. The clock can be delayed up to 38.4 ns in .15 ns steps and fine delayed up to 2.2 ns in 20 ps steps. The Phenix 9.4 Mhz Clock is distributed to the 32 T&C Modules via MC100E111 Differential Clock Drivers. A second source for the Phenix 9.4 Mhz Clock is a 300 mhz osc. going through divide by 12 logic to produce a 9.4 mhz clock which is distributed as above. Phenix set start and set stop are initiated by the on line group and synched to the Phenix 9.4Mhz clock in the Master Timing Module and then sent to the 32 T&C Modules. The Phenix Fiducial Clock has two sources. One being the RHIC Fiducial Clock and the second being a counter set to output a 106 ns pulse at the count of 120(# of RHIC Beam crossings). The counter is clocked by the Phenix 9.4 mhz Clock. The 32 bits of Lvl-1 trigger are received through an input Transition Module and driven onto the VME64 Backplane. Each of the eight output Transition Modules contain 4 cables to 4 T&C Modules. The 20 required signals to each T&C Module are received from the VME64 Backplane and driven to the T&C Modules via National LVDS Differential Line Drivers.


3.0 Master Timing, Start/Stop and Fiducial Module Registers

Base+00h R 0..15 Module ID 
Base+02h R 0..15 Serial Number
Base+100h R/W 0..8 Fiducial Counter Input Stage  On Bits 0..8 
Normally set for 120  counts of 9.38MHZ ="0x88"
Base+102h R/W 0..7 Set Course Delay for 9.38MHZ Clock (0.15ns steps)
Base+104h R/W 0..6 Set Fine Delay for 9.38Mhz Clock (20ps steps)
Base+106h R/W 0..1 Set  1/4 Delay for 9.38Mhz  Clock 
(0 =  0 clock shift)
(1= 1/4 clock shift)
(2=2/4 clock shift)
(3=3/4 clock shift)
Base+108h R/W 0 0 = 9.38Mhz Oscillator, 1 = RHIC 9.38Mhz
Base+108h R/W 1 9.38 RHIC clock check  0 =  ON 1 = OFF
Base+10Ah  R/W 0 Start Command From ONCS 
Base+10Ah R/W 1 Stop Command From ONCS 
Base+10Ch W 0 1 = Load Fiducial Counter Output Stage With 
Count On Input Stage .
Base+10Ch R/W 1 Fiducial Output Select .. 
      0 = On Board Fiducial Counter 
1 = RHIC Fiducial Selected 
Base+10Eh W ---- Reset Board  (writing anything  to this location causes the board to reset).

3.1  FRONT PANEL LED's

LED # Function  
1
 Altera pld check #1 ON = fail   OFF = pass
2
Altera pld check  #2 ON = fail   OFF = pass
3
Fiducial indicator ON = internal OFF = RHIC
4
START ON = in start mode
5
STOP ON = in stop mode
6
RHIC CLK indicator ON = internal CLK OFF = RHIC
7
CLK FREQ. CHECK OFF = freq. is between 8.9MHZ and 9.7Mhz


4.0 Master Timing System Block Diagrams

Figure 1. Block Diagram of Start, Stop, Fidclk,Level1
 
 
 
 


Figure
2. Block Diagram of RHIC 9.4Mhz and Local 9.4Mhz Oscillator




Please report any problems to  Jack Fried