After VCC stable, SEB will begin to program its on board Altera PLD by downloading Bit Patterns store in an EEPROM. Upon completion of programming, SEB pulls NREADY low if the CLOCK is running and RESET is low.
The DCM must monitor the HOLD signal from SEB at every rising edge of the CLOCK, and to act accordingly. The DCM may begin to assert VALID and send out DATA after it detects that HOLD is low at rising edge of the CLOCK. The DCM should guarantee that the data is stable at every rising edge of the clock.
Fast Data Transfer on the SEB:
The SEB has 2 banks of memory. When one bank is almost full ( there are multiple schemes to determine an almost full alarm) the SEB swaps in the other bank of memory. It then generates an interrupt to begins a scatter gather DMA transfer and empties out the memory.
What if both banks are Full?
If both banks are full (one banks is full while the other is transferring data using DMA) the SEB will assert the HOLD line till one bank is empty and continue the data collection.